PCB electroplating defects include missing copper in holes, uneven deposit thickness, nodules, pits, peeling, and cracks. They can cause immediate electrical failures or leave weaknesses that emerge during assembly and service. For engineers and purchasing teams, the immediate challenge is deciding whether a suspect lot meets its requirements and what evidence supports the supplier’s proposed correction.
Effective troubleshooting starts with the defect’s location and the process stage where it first appears. A void found after electroplating may originate in drilling, desmear, or initial hole metallization. Simply increasing plating time or adding chemicals can leave the underlying problem unresolved.
This guide focuses on electrolytic copper in PCB fabrication. It explains how to distinguish common defects, choose useful confirmation tests, and specify inspection evidence before accepting replacement or corrected boards.
Electroplating uses electrical current to deposit metal onto a conductive surface. In a conventional plated-through-hole process, drilling and hole preparation precede a conductive seed layer, often electroless copper, followed by electrolytic copper buildup. Direct metallization provides an alternative conductive preparation route.
A defect may affect the panel surface, hole wall, hole entrance, or connection to an internal copper layer. Record the exact location: these features experience different preparation conditions, solution access, and current distribution.
Separate copper fabrication defects from surface-finish and soldering problems. Solder-joint voiding after reflow is a different investigation from missing copper in a hole barrel. If the symptom appears only in solder deposits, review paste transfer and the relevant PCB stencil before attributing it to electroplating.
Use the following table to prioritize investigation. Each cause is a hypothesis requiring confirmation; the table does not establish acceptance criteria or prescribe chemical additions.
| Observed defect | Causes to investigate | Evidence to request | Corrective direction |
|---|---|---|---|
| Missing copper or PTH voids | Incomplete initial metallization, poor hole preparation, trapped gas, inadequate solution exchange | Cross-sections showing defect location; coverage evidence before electrolytic buildup | Correct the earliest failing operation; verify wetting, preparation, and metallization |
| Thin hole-wall or entrance copper | Poor throwing power, local current distribution, geometry beyond the qualified process | Thickness measurements at defined barrel and entrance positions; panel location map | Review chemistry, solution movement, current recipe, and panel configuration together |
| Nodules or rough deposits | Particles, residues, additive imbalance, anode-related contamination | Surface microscopy; sections through protrusions; filtration and bath-control records | Identify whether growth begins around debris or reflects deposit chemistry |
| Pits or localized depressions | Gas shielding, poor wetting, surface contamination | Surface and cross-sectional images; correlation with panel orientation | Verify cleaning, wetting, and solution movement before changing the recipe |
| Peeling or blistering | Contamination, inadequate preparation, weak interfaces | Section or failure analysis locating the separation interface | Correct the preparation or interface responsible; verify adhesion after correction |
| Barrel or corner cracks | Local thin copper, inadequate deposit properties, construction-related thermal strain | Sections before and after agreed thermal exposure | Evaluate copper distribution, deposit properties, and board construction |
| Voids inside copper-filled vias | Inadequate filling behavior for the geometry or process conditions | Sections through representative filled features | Qualify the filling process for the actual via geometry |
A surface photograph can identify a symptom. It rarely establishes whether the defect affects the complete conductive path.
Continuous copper buildup depends on an adequately prepared, conductive hole wall. Resin smear, poorly conditioned surfaces, or incomplete seed coverage can leave regions where subsequent plating cannot reliably develop.
The University of Maryland’s CALCE explanation of plating voids identifies inadequate conditioning, acceleration, and catalyzation as possible causes of missing electroless copper coverage. CALCE also explains that voids can concentrate stress and contribute to cracking during temperature cycling or vibration. Center for Advanced Life Cycle Engineering
The practical implication is to compare evidence from successive stages. Ask whether the discontinuity existed before electrolytic copper was deposited. A supplier that can demonstrate good initial coverage has narrowed the investigation; a final section alone may not establish when the defect began.
For multilayer PCBs, pay particular attention to the interfaces between the plated barrel and internal copper layers. A defect at an interconnect requires a different investigation from an isolated surface pit.
Trapped gas can shield a local region from solution contact. Solution movement that looks adequate at the panel surface may still provide poor exchange inside a narrow hole.
Ask the fabricator to correlate void locations with hole geometry, rack position, panel orientation, and process stage. A repeatable pattern helps distinguish a local transport problem from widespread preparation failure. Treat these correlations as diagnostic clues, then confirm the proposed mechanism through controlled trials.
Nodules are raised deposits; pits are depressions. General roughness may contain several kinds of irregular growth. Grouping all three as a single cosmetic issue can lead to an ineffective correction.
Michael Carano’s original case study of plating nodules in two cells describes different roughness mechanisms at one fabricator: additive control in one case, and filtration and anode maintenance in the other. The account demonstrates why similar visible symptoms do not establish a shared cause. iconnect007.com
For a nodule, request a section showing whether copper grew around an inclusion. Compare affected cells and inspect relevant filtration, anode, and preparation records. For pits, prioritize whether the affected surface was clean and consistently wetted. Avoid a generic instruction to add brightener: the bath may already be imbalanced.
Disposition also depends on function. A protrusion inside a finished hole can reduce insertion clearance even when continuity passes. Check the lead or pin dimensions of the affected PCB components against the specified finished-hole requirements, including any press-fit constraints.
Copper deposition depends on local current distribution and access to the electrolyte. Surface copper, hole entrances, and barrel centers need not receive equal deposits. A satisfactory surface measurement therefore does not prove adequate copper throughout a hole.
Three decision factors deserve separate review.
Throwing power concerns the process’s ability to distribute deposited copper into recessed features relative to exposed surfaces. When comparing supplier data, ask how the reported ratio is calculated and where thickness was measured.
Aspect ratio is relevant, but its basis matters. For a through-hole process, specify whether the diameter used is the drilled opening or the finished plated hole. For a blind feature, use the relevant feature depth. Avoid comparing ratios calculated from different geometries.
Local copper density and the manufacturing panel can influence plating distribution. During PCB layout review, identify dense and sparse regions and ask whether panel positioning or approved copper thieving would help.
Any added copper must respect electrical clearances, controlled-impedance features, and assembly constraints. A manufacturing adjustment should pass the same design-change controls as other artwork changes.
Chemistry and equipment operate as a system. Atotech’s Cupracid TP5 technical description specifies a DC conformal copper process with a leveller, brightener, and carrier monitored using cyclic voltammetric stripping, or CVS. This is evidence for one defined process, rather than a universal recipe for every plating line. Atotech
Request the supplier’s qualified operating window for the proposed construction. Increasing current can shorten deposition time while worsening local distribution if the process cannot support it. Changing agitation without checking the installed chemistry and equipment may also fail to address the limiting factor.
Extra plating can help when the confirmed problem is insufficient buildup over sound, continuous metallization. It does not reliably repair contamination, a weak interface, or an isolated region without adequate conductive preparation.
More deposit can also reduce finished-hole clearance and increase the processing burden for fine outer-layer features. The buyer should therefore specify the required copper condition at the critical location, alongside finished dimensions, rather than requesting an arbitrary increase everywhere.
Consider this illustrative situation: surface copper meets its target, but a barrel center is thin. Extending the cycle may add substantial surface copper before the center becomes acceptable. A change in geometry, distribution, or the qualified plating process may offer a better result. The choice requires measured trial data.
Involve PCB design review when the construction repeatedly approaches the fabricator’s demonstrated process limits. A larger drilled opening or revised stack-up can sometimes reduce manufacturing difficulty, but routing density and product dimensions may constrain those options.
Locate the failure interface before choosing a corrective action. Separation between deposited copper and underlying copper points toward different process questions from separation near the dielectric or an internal interconnect.
For peeling, preserve evidence before polishing, stripping, or reworking suspect boards. Ask what was contaminated, whether cleaning and activation were effective, and whether the initial conductive preparation remained intact through subsequent processing.
For cracks, examine both local copper thickness and the strain imposed by the board construction and thermal history. A crack revealed after reflow does not by itself prove that the assembly profile was the original cause. Equally, its timing does not establish that electroplating alone was responsible.
Coordinate fabrication evidence with the actual PCB assembly profile, reflow exposure, and rework history. Evaluate the construction under the agreed conditions rather than a generic temperature test selected after a failure.
Copper-filled microvias require their own investigation: an internal fill void and a discontinuity in conformal hole-wall plating describe different structures. Evidence for one structure should not be used to qualify the other.
No single inspection method answers every plating question. Choose the method according to the suspected failure and the decision it must support.
| Method | Useful question it can answer | Limitation to recognize |
|---|---|---|
| Surface optical inspection or AOI | Where are visible pits, nodules, or surface irregularities? | Cannot fully assess buried hole-wall conditions |
| Metallographic microsection | What are the local thickness, interfaces, voids, or cracks at this plane? | Destructive and limited to the sampled location and section plane |
| Electrical continuity testing | Does the tested connection conduct under the test conditions? | Does not establish adequate copper thickness or future thermal endurance |
| Agreed thermal exposure followed by evaluation | Does the sampled construction show damage or resistance change after that exposure? | Results depend on the profile, sample, measurement, and acceptance plan |
| Bath analysis and process records | Did documented process conditions remain within the qualified window? | Process compliance alone does not establish acceptance of every board |
Eurocircuits’ explanation of PTH microsection inspection describes using production coupons to inspect plated-hole quality and measure copper thickness. Its published examples also connect nodule assessment with surrounding structure, thickness, and finished-hole dimensions. These are manufacturer examples, not acceptance rules to copy into every contract. Eurocircuits
Ask for a report that identifies the lot, coupon, panel position, hole type, measurement locations, image scale, and acceptance basis. A conveniently located coupon may not represent the hardest feature on the product; the supplier should explain why the sampling plan is appropriate.
If continuity is disputed, identify the affected net against the PCB schematic and the released test data. This connects physical evidence to circuit function without treating electrical testing as a substitute for structural examination.
Put suspect material on hold while the responsible engineering and quality teams assess conformity. Separate the immediate lot decision from the longer-term process correction.
A useful supplier response should identify:
Use the agreed PCB quality control requirements to define the release evidence. A statement that the bath was adjusted is insufficient when the original issue was a hidden barrel defect.
For a new RFQ or replacement order, provide the released fabrication files, stack-up, material specification, board thickness, drill data, finished-hole sizes, and copper requirements. Distinguish surface copper from deposited hole-wall copper and distinguish conformal plating from copper filling.
State the applicable acceptance standard, revision, performance class where relevant, and drawing-specific requirements. Define coupon coverage, inspection reporting, thermal evaluation, lot traceability, quantity, and required delivery date. Avoid asking a supplier to infer these requirements from a general request for “high reliability.”
Compare quotations against the same evidence package. Additional coupons, destructive analysis, qualification builds, or replacement production consume time and material. Request separate pricing and schedule implications so a low initial board price does not conceal the cost of verification or delay.
Before authorizing production, ask the supplier to identify the most difficult plated feature in the design and show how its process and inspection plan address that feature.
Common defect categories include hole-wall voids, thin or uneven copper, nodules, pits, peeling, and cracks. Copper-filled vias can also contain internal voids. The relevant risk depends on defect location, board construction, and the agreed acceptance requirements.
No. Incomplete hole preparation or initial metallization can create a discontinuity before electrolytic buildup. Compare evidence from successive process stages to determine when the defect first appeared, rather than identifying the responsible operation from the final inspection alone.
Longer plating can increase thickness on an adequately prepared conductive surface. It does not reliably repair an isolated area with poor initial coverage or a weak interface. Confirm the mechanism and dimensional consequences before approving extra plating as a correction.
Specify the required copper at the relevant surface, barrel, or other feature, using the agreed standard, class, and drawing requirements. Distinguish minimum local thickness from an average or nominal target. No single value suits every construction and acceptance basis.
Yes. A connection can conduct during testing while containing locally thin copper or another structural weakness. Electrical testing, representative microsections, and any agreed thermal evaluation answer different questions and should be selected according to the product’s requirements.
Rework requires a defined method, authorization where applicable, and evidence that the finished board meets structural and dimensional requirements. Hidden voids or weak interfaces may remain unresolved by additional plating. Replacement is appropriate when conformity cannot be demonstrated.
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