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<\/figure>\n\n\n\nWhat Does PCB EMC Design Actually Control?<\/h2>\n\n\n\n
Electromagnetic compatibility, or EMC, covers both limiting unwanted emissions and maintaining acceptable operation in the presence of electromagnetic disturbances. EMI describes the interference itself.<\/p>\n\n\n\n
A useful review identifies three elements: a source, a coupling path, and a receiver. A switching regulator may generate noise; shared supply impedance, electric or magnetic fields, or a cable may transfer it; an ADC input or another product may receive it.<\/p>\n\n\n\n
Conducted and radiated describe how energy travels. Differential-mode and common-mode describe current relationships. These are different classifications: common-mode current on an external cable, for example, can produce radiated emissions.<\/p>\n\n\n\n
Use those distinctions to write a specific problem statement. \u201cNoise appears at the sensor input when the regulator switches\u201d gives the reviewer a starting point. \u201cThe PCB has bad EMC\u201d does not.<\/p>\n\n\n\n
Record the operating environment, interfaces, and acceptable behavior in the PCB design<\/a> brief. Treat the board, firmware, enclosure, and connected equipment as one test configuration.<\/p>\n\n\n\n Before routing, agree which operating modes matter: maximum processing activity, communication traffic, motor switching, startup, standby transitions, and realistic loads. A quiet demonstration mode may miss the condition that creates the largest disturbance.<\/p>\n\n\n\n Have the responsible compliance specialist identify the applicable product standards, markets, editions, emissions classes, and immunity criteria. There is no universal EMC limit that applies to every bare PCB.<\/p>\n\n\n\n During the PCB schematic<\/a> review, identify:<\/p>\n\n\n\n Make ownership explicit. A fabrication quotation, layout review, and system EMC assessment are different scopes. Ask which deliverables and measurements each quotation includes.<\/p>\n\n\n\n Layer count alone does not determine EMC performance. The more useful question is whether critical signals have nearby, continuous reference conductors throughout their routes.<\/p>\n\n\n\n Infineon\u2019s board-layout EMC guidance<\/a> explains how interrupted high-speed return paths enlarge current loops. It also identifies signal rise and fall times as relevant to the frequency content that layout must accommodate.<\/p>\n\n\n\n For a multilayer design, identify the reference plane for each critical routing layer before placement. Check plane continuity beneath connector escapes, dense via fields, and transitions. An apparently solid plane can contain a narrow neck or a row of clearances that forces a return-current detour.<\/p>\n\n\n\n For a two-layer design, review whether routing leaves sufficiently continuous return copper. If preserving that copper requires long detours or difficult placement compromises, request a multilayer alternative.<\/p>\n\n\n\n The purchasing decision should compare finished stackups and routing constraints, rather than layer count in isolation. Ask the fabricator to confirm dielectric thicknesses, material assumptions, impedance requirements, and whether proposed substitutions change the approved geometry.<\/p>\n\n\n\n When evaluating PCB products<\/a>, use a project-specific construction specification. A generic board category cannot demonstrate that a proposed stackup preserves your return paths.<\/p>\n\n\n\n During PCB layout<\/a> review, annotate how a critical signal\u2019s reference changes when it passes through a via.<\/p>\n\n\n\n Where both references are the same ground net, a nearby ground connection can provide a return transition. Where references differ, the solution needs circuit and stackup analysis; adding a ground via alone does not connect different reference nets.<\/p>\n\n\n\n Never bridge a required isolation barrier merely to provide an EMC shortcut. Include safety clearances and isolation requirements in the review constraints.<\/p>\n\n\n\n Separate noisy power stages, digital processing, and sensitive analog functions through placement and routing. Keep their local current paths from sharing avoidable impedance.<\/p>\n\n\n\n Separate AGND and DGND pin names do not automatically require separate board planes. Analog Devices\u2019 MT-031 grounding tutorial<\/a> explains this distinction and shows a low-digital-current converter arrangement in which both pins connect locally to the analog ground plane. It also discusses other system grounding arrangements.<\/p>\n\n\n\n The practical recommendation is to choose the grounding architecture from actual current flow and the selected device\u2019s requirements. A continuous reference is a useful starting point for many boards, while precision analog systems, isolation boundaries, and particular power architectures may require different treatment.<\/p>\n\n\n\n Ask the reviewer to show where digital interface currents, analog input returns, and power-stage currents flow. If the explanation depends only on labels such as \u201cclean ground\u201d and \u201cdirty ground,\u201d request a current-path drawing before approving the split.<\/p>\n\n\n\n For a buck converter, trace the current paths during both switching states. The path whose current changes abruptly deserves particular attention; making every power trace equally wide does not identify that path.<\/p>\n\n\n\n Texas Instruments\u2019 AN-2155 converter-layout report<\/a> explains the high-di\/dt loop and the input bypass capacitor\u2019s role. It also describes coupling from the switch node and the efficiency trade-off involved in slowing switching transitions.<\/p>\n\n\n\n Use the regulator manufacturer\u2019s layout as a starting point, then review differences introduced by your board geometry, connector positions, and thermal constraints.<\/p>\n\n\n\n For approval, request a marked drawing of the commutating loop. Check the input capacitor, switching devices, and their connections together rather than judging each component independently.<\/p>\n\n\n\n Keep sensitive traces and feedback routing away from the switch node. Review any proposed copper enlargement with both electrical and thermal requirements in view.<\/p>\n\n\n\n A compact electrical layout may still need a separate heat-spreading strategy. Conversely, increasing copper because a device runs warm can change coupling to nearby circuitry. Ask the designer to document how the chosen layout addresses both concerns.<\/p>\n\n\n\n If damping or slower switching is proposed, require temperature, efficiency, and waveform checks alongside the emissions measurement. A quieter spectrum alone is insufficient evidence that the revised power stage is ready.<\/p>\n\n\n\n A capacitor\u2019s schematic value does not describe its installed behavior. The relevant path includes the power pin, capacitor, return connection, and any vias.<\/p>\n\n\n\n MT-031 shows how local supply decoupling can confine a converter\u2019s transient digital current. That supports reviewing the physical loop rather than approving a capacitor simply because it is drawn near an IC.<\/p>\n\n\n\n For each critical supply, ask the reviewer to identify the local capacitor and trace the complete connection. Then check the selected package, effective capacitance under bias, and impedance behavior against the device requirements.<\/p>\n\n\n\n During PCB components<\/a> review, record which electrical characteristics approved alternates must preserve. Matching nominal capacitance and package size may leave important differences unresolved.<\/p>\n\n\n\n Avoid specifying a collection of capacitor values without a reason. If the power distribution network shows ringing or unexpected impedance peaks, investigate the network and its parasitics before adding more parts.<\/p>\n\n\n\n A low repetition rate does not guarantee a slow electrical edge. Review driver slew rate, loading, transmission-line behavior, and receiver timing together.<\/p>\n\n\n\n Where supported by the interface, adjustable drive strength or source termination may be useful. Select and verify those changes against waveform quality and timing requirements; do not assign one resistor value to every digital net.<\/p>\n\n\n\n For differential interfaces, review asymmetry through the whole channel: package escape, vias, protection components, connector, and cable. Length matching alone is an incomplete review.<\/p>\n\n\n\n At each external connection, define the intended signal return and shield or chassis connection. Place candidate filters so that their routing does not create an obvious coupling path around them.<\/p>\n\n\n\n Treat connector-side filters as part of a particular interface design. A common-mode choke needs suitable current capacity and signal performance, while protection devices need appropriate electrical characteristics and a defined discharge path.<\/p>\n\n\n\n The following table gives qualitative investigation priorities, not guaranteed diagnoses.<\/p>\n\n\n\nStart With Requirements and the Schematic<\/h2>\n\n\n\n
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Choose the Stackup Around Return Paths<\/h2>\n\n\n\n
Plan the Return at Every Layer Transition<\/h3>\n\n\n\n
Partition Circuits Without Automatically Splitting Ground<\/h2>\n\n\n\n
Reduce Switching Noise at Its Source<\/h2>\n\n\n\n
Identify the Commutating Loop<\/h3>\n\n\n\n
Balance Switch-Node Area Against Thermal Needs<\/h3>\n\n\n\n
Review Decoupling as a Complete Connection<\/h2>\n\n\n\n
Control Signal Edges, Connectors, and Cables<\/h2>\n\n\n\n
Choose Mitigation From the Measured Symptom<\/h2>\n\n\n\n